Lib.rs

› Hardware support › RustHDL
#verilog #fpga #hardware

yanked rust-hdl-test-core

Test infrastructure for the RustHDL crate

was by basusamit and 3 contributors. Owned by Samit Basu.

0.1.0 Oct 22, 2021

#68 in #verilog


Used in rust-hdl-test-ok-common

MIT license

130KB
3.5K SLoC

This repository is no longer maintained.

Dependencies

~6MB
~121K SLoC