Lib.rs

› Hardware support › RustHDL
#verilog #fpga #hardware

yanked rust-hdl-test-core

was by Samit Basu and 3 contributors

0.1.0 Oct 22, 2021

#73 in #verilog


Used in rust-hdl-test-ok-common

MIT and AGPL-3.0-only

130KB
3.5K SLoC

Test infrastructure for the RustHDL crate

Dependencies

~6.5MB
~126K SLoC