Lib.rs

› Hardware support › RustHDL
#verilog #hardware #fpga

yanked rust-hdl-sim-chips

was by Samit Basu and 3 contributors

0.1.0 Oct 22, 2021

#73 in #verilog


Used in 2 crates

MIT license

61KB
1.5K SLoC

Chip simulations for testing in RustHDL

Dependencies

~6MB
~117K SLoC