Lib.rs

› Hardware support › RustHDL
#fpga #verilog #hardware

yanked rust-hdl-sim-chips

was by basusamit and 3 contributors. Owned by Samit Basu.

0.1.0 Oct 22, 2021

#71 in #verilog


Used in 2 crates

MIT license

61KB
1.5K SLoC

Chip simulations for testing in RustHDL

Dependencies

~6MB
~115K SLoC