Lib.rs

GateConvertExec

The program allows to easily convert Gate circuit from/to one of few foreign formats.

Sample usage:

gateconvert COMMAND INPUT OUTPUT [PARAM1] [PARAM2]...

COMMAND is name of command. INPUT is path to input file. OUTPUT is path to output file. PARAM1, PARAM2,... are optional parameters.

List of commands:

• from-cnf - convert from DIMACS CNF.
• to-cnf - convert to DIMACS CNF.
• from-aiger - convert from AIGER.
• to-aiger - convert to AIGER.
• to-btor2 - convert to BTOR2.
• from-blif - convert from BLIF.
• to-blif - convert to BLIF.
• to-verilog - convert to Verilog.
• to-vhdl - convert to VHDL.

About mapping files

Mapping files are text files with variable mapping into output circuit wire. Entry in mapping file is single line.

Simplest format of line of mapping file: {circuit_input|-} - circuit input or '-' if no assignment.

Next format of line of mapping file (for conversion from AIGER): {var_index} {[!]circuit_wire|false|true|-} var_index - variable index. circuit_wire - circuit wire index. '-' - no input.

Simplest format of line of mapping file (for conversion from BLIF): {var_name} {[!]circuit_wire|false|true|-} var_name - variable index. circuit_wire - circuit wire index. '-' - no input.

More informations in help in same program.