#parser #verilog #systemverilog

app mdbook-veryl

A modern hardware description language

5 releases

new 0.3.1 Jan 30, 2023
0.3.0 Jan 27, 2023
0.2.2 Jan 24, 2023
0.2.1 Jan 19, 2023
0.2.0 Jan 16, 2023

#46 in Hardware support

Download history 45/week @ 2023-01-15 46/week @ 2023-01-22

91 downloads per month


50K SLoC


Veryl is a modern hardware description language.

This project is under the exploration phase of language design. If you have any idea, please open Issue.

Actions Status Crates.io Changelog


Veryl is designed as a "SystemVerilog Alternative". There are some design concepts.

Symplified Syntax

Veryl has symplified syntax based on SystemVerilog / Rust. "Symplified" has two meanings. One is for parser, and another is for human.

SystemVerilog has very complicated syntax (see IEEE Std 1800-2017 Annex A). This causes difficulty of SystemVerilog tool implementation. So Veryl should have simple syntax to parse. For example, "off-side rule" like Python, "automatic semicolon insertion" like ECMAScript / Go will not be supported.

SystemVerilog has various syntax. Some syntaxes are inherited from Verilog, and some syntaxes are added from SystemVerilog. Additionally some syntaxes can be written, but cannot be used actually because major EDA tools don't support them. So user should learn many syntaxes and whether each syntax can be used or not. Veryl will not support old Verilog style, unrecommended description, and so on.

Transpiler to SystemVerilog

HDL alternative languages should be transpiler to the tradisional HDLs like Verilog / VHDL because major EDA tools support them. Veryl is a transpiler to SystemVerilog.

Transpiler to Verilog has wide EDA tool support including OSS EDA tools. But even if there are rich data strucuture like struct / interface in HDL alternatives, transpiled Verilog can't have it. If HDL alternatives have rich code generateion mechanism, transpiled Verilog will be expanded to the very long code. For these reason, debugging the transpiled code becomes difficult.

Veryl will has almost all the same semantics as SystemVerilog. So transpiled code will be human readable SystemVerilog.

Additionally Veryl have interoperability with SystemVerilog. Veryl can use SystemVerilog's module / interface / struct / enum in the code, and vice versa.

Integrated Tools

Modern programming languages have development support tools like linter, formatter, and language server by default. Veryl will have them too from the beginning of development.

The following tools are planed to support.

  • Semantic checker
  • Source code formatter
  • Language server
  • Package manager


Download binary

Download from release page, and extract to the directory in PATH.


You can install with cargo.

cargo install veryl veryl-ls


  • Create a new project
veryl new [project name]
  • Create a new project in an existing directory
veryl init [path]
  • Format the current project
veryl fmt
  • Analyze the current project
veryl check
  • Build target codes corresponding to the current project
veryl build


Source Code

Veryl: https://github.com/dalance/veryl/tree/master/testcases/vl

Transpiled SystemVerilog: https://github.com/dalance/veryl/tree/master/testcases/sv

Package Configuration

name = "name"      # project name
version = "0.1.0"  # project version (semver is recommended)

clock_type    = "posedge"    # default clock type [posedge|negedge]
reset_type    = "async_low"  # default reset type [async_low|async_high|sync_low|sync_high]
filelist_type = "absolute"   # filelist type [absolute|relative|flgen]

# output target files in the same location as source
target     = {type = "source"}

# output target files in the specified directory
#target     = {type = "directory", path = "testcases/sv"}

indent_width = 4  # indent width



Licensed under either of

at your option.


Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any additional terms or conditions.


~362K SLoC