49 releases (12 breaking)
new 0.13.3 | Nov 25, 2024 |
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0.13.0 | Sep 12, 2024 |
0.11.1 | Jul 3, 2024 |
0.8.1 | Mar 14, 2024 |
0.1.3 | Dec 23, 2022 |
#681 in Hardware support
155 downloads per month
Used in 4 crates
3MB
72K
SLoC
Veryl is a modern hardware description language.
This project is under the exploration phase of language design. We call for the following suggestion or contribution:
- Language design
- Tool implementation
- Standard library implementation
If you have any idea, please open Issue or Pull request.
External resources
Documentation quick links
Overview
Veryl is a hardware description language based on SystemVerilog, providing the following advantages:
Optimized Syntax
Veryl adopts syntax optimized for logic design while being based on a familiar basic syntax for SystemVerilog experts. This optimization includes guarantees for synthesizability, ensuring consistency between simulation results, and providing numerous syntax simplifications for common idioms. This approach enables ease of learning, improves the reliability and efficiency of the design process, and facilitates ease of code writing.
Interoperability
Designed with interoperability with SystemVerilog in mind, Veryl allows smooth integration and partial replacement with existing SystemVerilog components and projects. Furthermore, SystemVerilog source code transpiled from Veryl retains high readability, enabling seamless integration and debugging.
Productivity
Veryl comes with a rich set of development support tools, including package managers, build tools, real-time checkers compatible with major editors such as VSCode, Vim, Emacs, automatic completion, and automatic formatting. These tools accelerate the development process and significantly enhance productivity.
With these features, Veryl provides powerful support for designers to efficiently and productively conduct high-quality hardware design.
Example
Veryl | SystemVerilog |
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FAQ
Why not SystemVerilog?
SystemVerilog is very complicated language, and it causes difficulty of implementing EDA tools for it. As a consequence, major EDA tools only support SystemVerilog subset which is different each other, and users must explore usable languege features which are covered by adopted tools. Additionally, the difficulty prevents productivity improvement by developing support tools. This is a reason that a new language having simplified and sophisticated syntax, not SystemVerilog, is required.
Why not existing Alt-HDLs (e.g. Chisel)?
Many existing alt-HDLs are inner DSL of a programming language.
This approach has some advantages like rapid development and resusable tooling ecosystem,
but the syntax can't be fit for hardware description completely.
Additionally, enormous Verilog code is generated from short and sophisticated code in these languages.
This prevents general ASIC workflows like timing improvement, pre/post-mask ECO because these workflows require FF-level modification in Verilog.
Interopration between these language and SystemVerilog is challenging because these can't connect to SystemVerilog's type like interface
and struct
directly.
By these reason, the existing Alt-HDLs can't be used as alternative of SystemVerilog, especially if there are many existing SystemVerilog codebase.
Veryl resolves these problems by HDL-specialized syntax and human-readable SystemVerilog code generation.
Why some language features (e.g. auto pipelining) are not adopted?
Veryl focuses equivalency with SystemVerilog at the point of view of the language semantics. This eases to predict the changes of generated SystemVerilog code from modification of Veryl code, and Veryl can be applied to ASIC workflows like timing improvement and pre/post-mask ECO. Therefore, some features generating FFs are not adopted because these prevent the predictability.
Why some syntax features (e.g. off-side rule, semicolon less) are not adopted?
Veryl focuses syntax simplicity because it reduces tool implementation effort. Therefore syntax features which introduce large complexity in exchange for slight abbreviation are not adopted.
Installation & Usage
See Getting Started.
Publications
- Naoya Hatta, Taichi Ishitani, Ryota Shioya. Veryl: A New Hardware Description Language as an Alternative to SystemVerilog. August 2024. In: The Design & Verification Conference (DVCon) Japan 2024. [Paper] [Slides] [arXiv]
License
Licensed under either of
- Apache License, Version 2.0, (LICENSE-APACHE or http://www.apache.org/licenses/LICENSE-2.0)
- MIT license (LICENSE-MIT or http://opensource.org/licenses/MIT)
at your option.
Contribution
Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any additional terms or conditions.
Dependencies
~20–33MB
~410K SLoC