5 releases
0.12.0 | Aug 21, 2024 |
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0.11.3 | Aug 9, 2024 |
0.11.2 | Aug 6, 2024 |
0.11.1 | Jul 3, 2024 |
0.11.0 | Jun 24, 2024 |
#2984 in Parser implementations
436 downloads per month
Used in 2 crates
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Veryl is a modern hardware description language.
This project is under the exploration phase of language design. If you have any idea, please open Issue.
Documentation quick links
Overview
Veryl is a hardware description language based on SystemVerilog, providing the following advantages:
Optimized Syntax
Veryl adopts syntax optimized for logic design while being based on a familiar basic syntax for SystemVerilog experts. This optimization includes guarantees for synthesizability, ensuring consistency between simulation results, and providing numerous syntax simplifications for common idioms. This approach enables ease of learning, improves the reliability and efficiency of the design process, and facilitates ease of code writing.
Interoperability
Designed with interoperability with SystemVerilog in mind, Veryl allows smooth integration and partial replacement with existing SystemVerilog components and projects. Furthermore, SystemVerilog source code transpiled from Veryl retains high readability, enabling seamless integration and debugging.
Productivity
Veryl comes with a rich set of development support tools, including package managers, build tools, real-time checkers compatible with major editors such as VSCode, Vim, Emacs, automatic completion, and automatic formatting. These tools accelerate the development process and significantly enhance productivity.
With these features, Veryl provides powerful support for designers to efficiently and productively conduct high-quality hardware design.
Example
Veryl | SystemVerilog |
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Installation
See Document.
Usage
// Create a new project
veryl new [project name]
// Create a new project in an existing directory
veryl init [path]
// Format the current project
veryl fmt
// Analyze the current project
veryl check
// Build target codes corresponding to the current project
veryl build
// Build the document corresponding to the current project
veryl doc
For detailed information, see Document.
License
Licensed under either of
- Apache License, Version 2.0, (LICENSE-APACHE or http://www.apache.org/licenses/LICENSE-2.0)
- MIT license (LICENSE-MIT or http://opensource.org/licenses/MIT)
at your option.
Contribution
Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any additional terms or conditions.
Dependencies
~5.5MB
~128K SLoC