vexide-devices

Functionality for accessing hardware connected to the V5 Brain.

This crate abstracts over the various V5 devices and provides a Peripherals API for accessing them.

lib.rs:

Hardware abstractions and functionality for peripherals on the V5 Brain.

Overview

This crate provides APIs for interfacing with VEX hardware and peripherals.

The V5 Brain features 21 RJ9 serial ports (known as "Smart Ports") for communicating with newer V5 devices, as well as six three-wire ports with analog-to-digital conversion capability for compatibility with legacy Cortex devices. The Brain also has a screen, battery, and usually a controller for reading user input.

Hardware access begins at the Peripherals API, where singleton access to the brain's I/O and peripherals can be obtained:

let peripherals = Peripherals::take().unwrap();

// Pull out port 1 of peripherals. This is a `SmartPort` and can be used to construct any
// device on port 1 of the Brain that we want to control.
let port_1 = peripherals.port_1;

If you are using vexide's #[vexide::main] macro, then Peripherals is already given to you through an argument to your main function:

#![no_std]
#![no_main]

use vexide::prelude::*;

#[vexide::main]
async fn main(peripherals: Peripherals) {
    println!("o.o what's this? {:?}", peripherals);
}

For more information on peripheral access, see the peripherals module.