page_table_multiarch

This crate provides generic, unified, architecture-independent, and OS-free page table structures for various hardware architectures.

The core struct is PageTable64<M, PTE, H>. OS-functions and architecture-dependent types are provided by generic parameters:

• M: The architecture-dependent metadata, requires to implement the PagingMetaData trait.
• PTE: The architecture-dependent page table entry, requires to implement the GenericPTE trait.
• H: OS-functions such as physical memory allocation, requires to implement the PagingHandler trait.

Currently supported architectures and page table structures:

• x86: x86_64::X64PageTable
• ARM: aarch64::A64PageTable
• RISC-V: riscv::Sv39PageTable, riscv::Sv48PageTable

Examples (x86_64)

use memory_addr::{MemoryAddr, PhysAddr, VirtAddr};
use page_table_multiarch::x86_64::{X64PageTable};
use page_table_multiarch::{MappingFlags, PagingHandler, PageSize};

use core::alloc::Layout;

extern crate alloc;

struct PagingHandlerImpl;

impl PagingHandler for PagingHandlerImpl {
    fn alloc_frame() -> Option<PhysAddr> {
        let layout = Layout::from_size_align(0x1000, 0x1000).unwrap();
        let ptr = unsafe { alloc::alloc::alloc(layout) };
        Some(PhysAddr::from(ptr as usize))
    }

    fn dealloc_frame(paddr: PhysAddr) {
        let layout = Layout::from_size_align(0x1000, 0x1000).unwrap();
        let ptr = paddr.as_usize() as *mut u8;
        unsafe { alloc::alloc::dealloc(ptr, layout) };
    }

    fn phys_to_virt(paddr: PhysAddr) -> VirtAddr {
        VirtAddr::from(paddr.as_usize())
    }
}

let vaddr = VirtAddr::from(0xdead_beef_000);
let paddr = PhysAddr::from(0x2000);
let flags = MappingFlags::READ | MappingFlags::WRITE;
let mut pt = X64PageTable::<PagingHandlerImpl>::try_new().unwrap();

assert!(pt.root_paddr().is_aligned_4k());
assert!(pt.map(vaddr, paddr, PageSize::Size4K, flags).is_ok());
assert_eq!(pt.query(vaddr), Ok((paddr, flags, PageSize::Size4K)));