#page-table #virtual-memory #paging #arceos

nightly no-std page_table_entry

Page table entry definition for various hardware architectures

10 unstable releases (3 breaking)

0.4.1 Oct 10, 2024
0.4.0 Aug 27, 2024
0.3.3 Aug 9, 2024
0.3.1 Jul 31, 2024
0.1.2 Jul 17, 2024

#339 in Hardware support

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Used in 3 crates

GPL-3.0-or-later OR Apache-2…

24KB
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page_table_entry

Crates.io Docs.rs CI

This crate provides the definition of page table entry for various hardware architectures.

Currently supported architectures and page table entry types:

All these types implement the GenericPTE trait, which provides unified methods for manipulating various page table entries.

Examples (x86_64)

use memory_addr::PhysAddr;
use x86_64::structures::paging::page_table::PageTableFlags;
use page_table_entry::{GenericPTE, MappingFlags, x86_64::X64PTE};

let paddr = PhysAddr::from(0x233000);
let pte = X64PTE::new_page(
    paddr,
    /* flags: */ MappingFlags::READ | MappingFlags::WRITE,
    /* is_huge: */ false,
);
assert!(!pte.is_unused());
assert!(pte.is_present());
assert_eq!(pte.paddr(), paddr);
assert_eq!(
    pte.bits(),
    0x800_0000000233_003, // PRESENT | WRITE | NO_EXECUTE | paddr(0x233000)
);

Dependencies

~695KB
~12K SLoC