aarch64 page table manipulation

This crate provides a library to manipulate page tables conforming to the AArch64 Virtual Memory System Architecture.

Currently it only supports:

• stage 1 page tables
• 4 KiB pages
• EL3, NS-EL2, NS-EL2&0 and NS-EL1&0 translation regimes

This is not an officially supported Google product.

License

Licensed under either of

• Apache License, Version 2.0 (LICENSE-APACHE or http://www.apache.org/licenses/LICENSE-2.0)
• MIT license (LICENSE-MIT or http://opensource.org/licenses/MIT)

at your option.

Contributing

If you want to contribute to the project, see details of how we accept contributions.

lib.rs:

A library to manipulate AArch64 VMSA page tables.

Currently it only supports:

• stage 1 page tables
• 4 KiB pages
• EL3, NS-EL2, NS-EL2&0 and NS-EL1&0 translation regimes

Full support is provided for identity mapping (IdMap) and linear mapping (LinearMap). If you want to use a different mapping scheme, you must provide an implementation of the Translation trait and then use Mapping directly.

Example

use aarch64_paging::{
    idmap::IdMap,
    paging::{Attributes, MemoryRegion, TranslationRegime},
};

const ASID: usize = 1;
const ROOT_LEVEL: usize = 1;
const NORMAL_CACHEABLE: Attributes = Attributes::ATTRIBUTE_INDEX_1.union(Attributes::INNER_SHAREABLE);

// Create a new EL1 page table with identity mapping.
let mut idmap = IdMap::new(ASID, ROOT_LEVEL, TranslationRegime::El1And0);
// Map a 2 MiB region of memory as read-write.
idmap.map_range(
    &MemoryRegion::new(0x80200000, 0x80400000),
    NORMAL_CACHEABLE | Attributes::NON_GLOBAL | Attributes::VALID | Attributes::ACCESSED,
).unwrap();
// SAFETY: Everything the program uses is within the 2 MiB region mapped above.
unsafe {
    // Set `TTBR0_EL1` to activate the page table.
    idmap.activate();
}