7 releases (4 breaking)
0.5.0 | Oct 25, 2023 |
---|---|
0.4.1 | Jun 16, 2023 |
0.4.0 | Apr 21, 2023 |
0.3.0 | Aug 15, 2022 |
0.1.0 | May 3, 2022 |
#699 in Embedded development
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105KB
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SLoC
aarch64 page table manipulation
This crate provides a library to manipulate EL1 page tables conforming to the AArch64 Virtual Memory System Architecture.
This is not an officially supported Google product.
License
Licensed under either of
- Apache License, Version 2.0 (LICENSE-APACHE or http://www.apache.org/licenses/LICENSE-2.0)
- MIT license (LICENSE-MIT or http://opensource.org/licenses/MIT)
at your option.
Contributing
If you want to contribute to the project, see details of how we accept contributions.
lib.rs
:
A library to manipulate AArch64 VMSA page tables.
Currently it only supports:
- stage 1 page tables
- EL1
- 4 KiB pages
Full support is provided for identity mapping (IdMap
) and linear mapping
(LinearMap
). If you want to use a different mapping scheme, you must
provide an implementation of the Translation
trait and then use
Mapping
directly.
Example
use aarch64_paging::{
idmap::IdMap,
paging::{Attributes, MemoryRegion},
};
const ASID: usize = 1;
const ROOT_LEVEL: usize = 1;
// Create a new page table with identity mapping.
let mut idmap = IdMap::new(ASID, ROOT_LEVEL);
// Map a 2 MiB region of memory as read-write.
idmap.map_range(
&MemoryRegion::new(0x80200000, 0x80400000),
Attributes::NORMAL | Attributes::NON_GLOBAL | Attributes::VALID,
).unwrap();
// SAFETY: Everything the program uses is within the 2 MiB region mapped above.
unsafe {
// Set `TTBR0_EL1` to activate the page table.
idmap.activate();
}
Dependencies
~120KB