#avr #decoder

yaxpeax-avr

AVR instruction set decoder for yaxpeax

4 releases

0.1.0 Jul 18, 2021
0.0.3 May 7, 2021
0.0.2 May 4, 2020
0.0.1 Apr 18, 2020
Download history 29/week @ 2022-04-24 28/week @ 2022-05-01 43/week @ 2022-05-08 73/week @ 2022-05-15 24/week @ 2022-05-22 37/week @ 2022-05-29 23/week @ 2022-06-05 3/week @ 2022-06-12 14/week @ 2022-06-19 14/week @ 2022-06-26 5/week @ 2022-07-03 9/week @ 2022-07-10 9/week @ 2022-07-17 18/week @ 2022-07-24 15/week @ 2022-07-31 18/week @ 2022-08-07

60 downloads per month
Used in yaxpeax-dis

0BSD license

40KB
675 lines

yaxpeax-avr

AVR decoders implemented as part of the yaxpeax project. Implements traits provided by yaxpeax-arch.

Known "issues"

  • The brbc and brbs instructions are displayed as their equivalent pseudo-instructions, based on the bit they test: brbc 0, label becomes brsh label. In this case specifically, brcc also exists (and is identical), however brsh will be displayed.
  • Target specification is limited to enabling/disabling support for 16-bit sts and lds instructions (as they can collide with other instructions cores with support for them don't have). Valid instructions (even if they might be unsupported by a core) are never rejected. Bytes which don't resemble an instruction from any instruction set subset are still invalid.

lib.rs:

AVR decoders implemented as part of the yaxpeax project. Implements traits provided by yaxpeax-arch.

Instruction set manual references are with respect to the document Atmel-0856-AVR-Instruction-Set-Manual.pdf as of 2020-04-13. sha256: dbf578218c9f52f2fd22ccc538f53b9db4890320835725678c02b7b58f641981

References to the ATmega48A/PA/88A/PA/168A/PA/328/P datasheet are with respect to the document ATmega48A-PA-88A-PA-168A-PA-328-P-DS-DS40002061A.pdf as of 2020-04-13. sha256: bf1c2e470f8ec7d4db340984f57556342557fed3eb9c457dd174b08db5993af6

Known "issues":

  • The brbc and brbs instructions are displayed as their equivalent pseudo-instructions, based on the bit they test: brbc 0, label becomes brsh label. In this case specifically, brcc also exists (and is identical), however brsh will be displayed.
  • Target specification is limited to enabling/disabling support for 16-bit sts and lds instructions (as they can collide with other instructions cores with support for them don't have). Valid instructions (even if they might be unsupported by a core) are never rejected. Bytes which don't resemble an instruction from any instruction set subset are still invalid.

Dependencies

~220KB