Lib.rs

xlsynth-g8r: gate-level infrastructure

xlsynth-g8r hosts the gate-level side of the xlsynth stack:

• aig: core AIG/GateFn representation and structural transforms (fraig, balancing, etc.).
• aig_serdes: (de)serialization to/from AIGER and a textual gate format.
• aig_sim: scalar and SIMD gate-level simulators.
• liberty / liberty_proto: Liberty parsing, indexing, and proto bindings.
• netlist: Verilog-like gate-level netlist parsing, connectivity, cone traversal, and GV→IR.
• transforms: local gate-level rewrite passes used by optimization and MCMC logic.

Most functionality is exposed via the xlsynth_g8r library and thin binaries under src/bin/.

Netlist parse benchmark

Run the synthetic netlist-parse microbenchmark with:

cargo bench -p xlsynth-g8r --bench netlist_parse_bench -- --verbose