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#31 in #system-verilog
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VLaDOS
(System)Verilog Language -- a Definitively Open Simulator
VLaDOS is a very early (and probably broken) alpha SystemVerilog compiler and simulator. The goals of the project are to:
- Compile code that adheres to the SystemVerilog LRM
- Act as a drop-in replacement for most other big-name compilers, such as Synopsys VCS, Mentor Questa, or Cadence Xcelium
- Remain free and open-source so that anyone can compile and run SystemVerilog code locally on any major computing platform