SiFive-Core

Low level access to SiFive processor cores.

MSRV of this crate is 1.59.0. Before that version is stabilized, you may need to build under nightly newer than 2021-12-15.

lib.rs:

Low level access to SiFive RISC-V processor cores

This crate provides:

• Access to core SiFive CSRs like bpm and feature disable;
• Access to assemble instructions like CEASE and cache control instructions;
• High level wrapper for handling SiFive platform features.