#risc-v #wch #low-level #ch32v

no-std qingke

Low level access to WCH's QingKe RISC-V processors

14 releases

0.2.0 May 11, 2024
0.1.11 Apr 28, 2024
0.1.9 Mar 27, 2024
0.1.5 Dec 24, 2023
0.1.0 Feb 19, 2023

#295 in Embedded development

Download history 193/week @ 2024-02-26 5/week @ 2024-03-04 155/week @ 2024-03-18 135/week @ 2024-03-25 66/week @ 2024-04-01 3/week @ 2024-04-08 131/week @ 2024-04-15 129/week @ 2024-04-22 80/week @ 2024-04-29 316/week @ 2024-05-06 61/week @ 2024-05-13 38/week @ 2024-05-20 35/week @ 2024-05-27 21/week @ 2024-06-03 17/week @ 2024-06-10

118 downloads per month
Used in 2 crates

MIT/Apache

16KB
339 lines

qingke & qingke-rt

Crates.io Crates.io docs.rs

Low level access to WCH's QingKe RISC-V processors.

qingke-rt

This crate provides the runtime support for QingKe RISC-V processors.

This provides riscv/riscv-rt like functionality, with the following differences:

  • Use vector table for interrupt handling
  • Handle 1KB address alignment for the entry point(Qingke V2)
  • In-SRAM code executing, highcode handling
  • PFIC support
  • Conflicts with riscv-rt crate

Usage

#[qingke_rt::entry]
fn main() -> ! {
    loop {}
}

// Or if you are using the embassy framework
#[embassy_executor::main(entry = "qingke_rt::entry")]
async fn main(spawner: Spawner) -> ! { ... }

#[qingke_rt::interrupt]
fn UART0() {
    // ...
}

#[qingke_rt::highcode]
fn some_highcode_fn() {
    // ...
    // This fn will be loaded into the highcode(SRAM) section.
    // This is required for BLE, recommended for interrupt handles.
}

Dependencies

~200–365KB