#risc-v #wch #ch32v #qingke

no-std qingke-rt

Minimal runtime / startup for WCH's RISC-V MCUs, managed by the ch32-rs team

12 releases

Uses new Rust 2024

0.6.1 Dec 8, 2025
0.5.0 Nov 3, 2024
0.2.1 May 14, 2024
0.1.9 Mar 27, 2024

#2399 in Embedded development

Download history 42/week @ 2025-11-13 95/week @ 2025-11-20 55/week @ 2025-11-27 340/week @ 2025-12-04 69/week @ 2025-12-11 96/week @ 2025-12-18 23/week @ 2025-12-25 47/week @ 2026-01-01 71/week @ 2026-01-08 41/week @ 2026-01-15 158/week @ 2026-01-22 95/week @ 2026-01-29 146/week @ 2026-02-05 27/week @ 2026-02-12 84/week @ 2026-02-19 108/week @ 2026-02-26

373 downloads per month
Used in 3 crates

MIT/Apache

41KB
964 lines

Differences vs the riscv-rt version

  • The structure of exception handlers is different
  • The structure of core interrupt handlers is different
  • Hardware stack push is available, so no need to push manually

qingke-rt

Replaces ch32v-rt as the name is not suitable for publishing.

QingKe is the name of the RISC-V core.

Usage

#[qingke_rt::entry]
fn main() -> ! {
    loop {}
}

// Or if you are using the embassy framework
#[embassy_executor::main(entry = "qingke_rt::entry")]
async fn main(spawner: Spawner) -> ! { ... }

#[qingke_rt::interrupt]
fn UART0() {
    // ...
}

// Interrupt provided by the IP core (not peripherals)
#[qingke_rt::interrupt(core)]
fn SysTick() {
    // ...
}

#[qingke_rt::highcode]
fn some_highcode_fn() {
    // ...
    // This fn will be loaded into the highcode(SRAM) section.
    // This is required for BLE, recommended for interrupt handles.
}

Dependencies

~2MB
~47K SLoC