#risc-v #wch #ch32v #qingke

no-std qingke-rt

Minimal runtime / startup for WCH's RISC-V MCUs, managed by the ch32-rs team

8 releases

0.2.1 May 14, 2024
0.2.0 May 11, 2024
0.1.12 May 9, 2024
0.1.11 Apr 28, 2024
0.1.7 Jan 1, 2024

#1915 in Embedded development

48 downloads per month
Used in ch58x-hal

MIT/Apache

37KB
892 lines

qingke-rt

Replaces ch32v-rt as the name is not suitable for publishing.

QingKe is the name of the RISC-V core.

Usage

#[qingke_rt::entry]
fn main() -> ! {
    loop {}
}

// Or if you are using the embassy framework
#[embassy_executor::main(entry = "qingke_rt::entry")]
async fn main(spawner: Spawner) -> ! { ... }

#[qingke_rt::interrupt]
fn UART0() {
    // ...
}

// Interrupt provided by the IP core (not peripherals)
#[qingke_rt::interrupt(core)]
fn SysTick() {
    // ...
}

#[qingke_rt::highcode]
fn some_highcode_fn() {
    // ...
    // This fn will be loaded into the highcode(SRAM) section.
    // This is required for BLE, recommended for interrupt handles.
}

lib.rs:

Differences vs the riscv-rt version

  • The structure of exception handlers is different
  • The structure of core interrupt handlers is different
  • Hardware stack push is available, so no need to push manually

Dependencies

~1.5MB
~39K SLoC