Xilinx AXI DMA Userspace Driver

This crates uses udmabuf and a generic userspace I/O driver (uio_pdrv_genirq) to interface Xilinx AXI DMA controllers. Please see this blog post and the example directory for further information.

Overview

The project is very much work-in-progress. At the moment, it only supports register mode transfers (i.e., no scatter gather). The crate supports sync and async operation.

Contributions

Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the project, shall be licensed as Apache 2.0, without any additional terms or conditions.