2 releases
0.1.1 | Apr 29, 2019 |
---|---|
0.1.0 | Apr 29, 2019 |
#1463 in Hardware support
Used in interrupture-stm32f7x6
20KB
213 lines
stm32f7-discovery
Building
- Install the thumbv7em-none-eabihf target: Run
rustup target add thumbv7em-none-eabihf
. - Run
cargo build
Running
First you need to install some dependencies:
- Install stlink: See https://github.com/texane/stlink#installation.
- Install openocd: At least version 0.10.0 is needed. You can install it either from your package manager or from source.
- Install gdb-multiarch: This cross-platform version of GDB should be available through your package manager.
Then you can connect your controller and run the following:
- Start openocd: In a separate terminal window, run
openocd -f board/stm32f7discovery.cfg
. You might needsudo
. If you get an "Can't find board/stm32f7discovery.cfg" error your version of openocd might be too old (it should be at least 0.10.0). - Run
cargo run
: This connects to the openocd instance and flashes your binary to the controller. - Continue execution: By default GDB pauses the execution after loading. To continue your program, run
continue
orc
.
To run in release mode (i.e. with optimizations), run cargo run --release
.
License
Licensed under either of
-
Apache License, Version 2.0 (LICENSE-APACHE or http://www.apache.org/licenses/LICENSE-2.0)
-
MIT license (LICENSE-MIT or http://opensource.org/licenses/MIT)
at your option.
Contribution
Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any additional terms or conditions.
lib.rs
:
Safe and "free of data races" interrupt system.
The interrupt system features are:
-
Ownership based interrupt management. The
InterruptTable
owns the nvic register and thus it is the only one that can access and change the interrupt controller. -
Easy to use closure-based ISR registration. Closures can be registered as interrupt service routine.
-
Free of data races. Thanks to Rust
Send
andSync
concept, the interrupt system is free of data races. Shared mutable access on a variable must be synchronized with a PrimaskMutex, otherwise the compilation fails. -
Scoped IRSs with access to the enviroment. It is guaranteed that the closure is unregistered at the end of the scope. Thus it is safe to access the parent stack in the interrupt service routine.
Dependencies
~31KB