Hecate Virtual Machine

This project provides an implementation of the Hecate virtual machine.

• Where does the name come from?
• ATTENTION
• Features
• Getting Started
  • Prerequisites
• Usage
• Performance Tracking
• Registers
• Bytecode Instruction Set
• Caches and Memory Access
  • Caches
  • Memory Access
    • Write Access
    • Read Access
      • Prefetching and Branch Prediction
• Sources

Where does the name come from?

The project is named Hecate, inspired by the ancient Greek goddess associated with magic, crossroads, and guiding transformations. Just as Hecate stood at the intersection of possibilities, this CPU project represents the convergence of computational logic, optimization, and problem-solving, providing participants with a structured yet flexible virtual machine to explore and optimize their solutions.

The name reflects both the mystical allure of programming challenges and the power of guiding complex tasks to completion.

ATTENTION

This project is currently unstable. Changes are to be expected. Use at your own risk!

Features

• Bytecode Execution:

  • Supports a well-defined set of instructions for computation, memory operations, and control flow.
  • Instructions include:
    • Arithmetic operations (Add, Sub, Mul, Div)
    • Memory access (LoadValue, LoadMemory, Store)
    • Stack manipulation (PushValue, PushReg, Pop)
    • Control flow (Call, Ret, Jmp)
    • Debugging (Inspect)
    • Halting (Halt)

• Performance Metrics:

  • Tracks the number of cycles executed.
  • Measures memory access performance using a multi-level cache scoring system (L1, L2, L3).

• Debugging and Verbose Mode:

  • NOT YET IMPLEMENTED Provides step-by-step debugging modes (StepOver, StepInto, StepOut) with support for code and data breakpoints.
  • Outputs detailed logs of executed instructions in verbose mode.

• Memory Model:

  • Flat memory structure with stack management.
  • Supports configurable memory size and register count.

Getting Started

Prerequisites

• Rust (for building the project)

Usage

1. Clone the repository: git clone cd

2. Run the demo project: cargo run --release -- run-asm demo.hasm

You can also use the provided assembler to produce bytecode by running cargo run -p hasm <input> <output>

Performance Tracking

The CPU tracks performance using the following stats:

Registers

When used as a library, the CPU can be instantiated with as many registers as desired.

When using the pre-made binary, the CPU has 31 general purpose registers. R1-R31. There is als a register called R0 which ignores writes and will always return 0.

Bytecode Instruction Set

For simplicity, this implementation operates on 32 bit unsigned integers. This might be changed later, but for now this should be enough.

Important: the cycle count mentioned here does not include memory access and is just for the instruction itself. For memory access cycle counts see the section below

Caches and Memory Access

Caches

Caching in this VM is simulated. This means the VM never actually copies values into a cache, it just remembers which memory locations are in which cache.

The VM uses hierarchical caching (L1, L2, L3) and has separate L1 caches for data (L1D) and instructions (L2D).

Memory Access

Write Access

In real hardware the CPU would write to cache and the hardware would eventually write back that value to main memory. As this process does not stall the CPU (AFAIK) the VM just assumes a cycle cost of 1.

Read Access

• L1 Cache Hit: 3 Cycles
• L2 Cache Hit: 11 Cycles
• L3 Cache Hit: 50 Cycles
• Main Memory: 125 Cycles

Prefetching and Branch Prediction

There is currently a simple prefetcher which fetches 2 cache lines of data on access and 10 lines of instructions. There is currently no branch predictor. Once there is, it will affect how prefetching works.

Sources

[^1]: IT Hare: Infographics: Operation Costs in CPU Clock Cycles