#verilog #rust-hdl #fpga

build extract_rust_hdl_interface

Extracts the information needed for a rust-hdl module from a verilog module

2 unstable releases

0.2.0 Jun 17, 2023
0.1.0 Mar 17, 2023

#523 in Build Utils


Used in 2 crates

MIT license

64KB
1.5K SLoC

generate_rust_hdl_module

This crate provides a extract_rust_hdl_interface function that extracts all the info you need to generate a rust-hdl module from a Verilog module.

The function does not actually generate code it just extracts the interface. It is mainly meant be used through the wrap_verilog! macro.


lib.rs:

generate_rust_hdl_module

This crate provides a extract_rust_hdl_interface function that extracts all the info you need to generate a rust-hdl module from a Verilog module.

The function does not actually generate code it just extracts the interface. It is mainly meant be used through the wrap_verilog! macro.

Dependencies

~4–5.5MB
~119K SLoC