#atomic #polyfill

no-std atomic-polyfill

Atomic polyfills, for targets where they’re not available

9 releases

0.1.8 Apr 12, 2022
0.1.7 Mar 22, 2022
0.1.6 Feb 8, 2022
0.1.5 Nov 2, 2021
0.1.2 Mar 28, 2021

#43 in Embedded development

Download history 14053/week @ 2022-03-14 15153/week @ 2022-03-21 18121/week @ 2022-03-28 17753/week @ 2022-04-04 15038/week @ 2022-04-11 13596/week @ 2022-04-18 15110/week @ 2022-04-25 16204/week @ 2022-05-02 17527/week @ 2022-05-09 17419/week @ 2022-05-16 17149/week @ 2022-05-23 16298/week @ 2022-05-30 18253/week @ 2022-06-06 19184/week @ 2022-06-13 15352/week @ 2022-06-20 17229/week @ 2022-06-27

70,821 downloads per month
Used in 288 crates (10 directly)


585 lines



This crate polyfills atomics on targets where they're not available, using critical sections. It is intended to be a drop-in replacement for core::sync::atomic.

There is three "levels" of polyfilling:

  • Native: No polyfilling is performed, the native core::sync::atomic::AtomicXX is reexported.
  • CAS: Only compare-and-set operations are polyfilled, while loads and stores are native.
  • Full: Both load/store and compare-and-set operations are polyfilled.

Target support

The right polyfill level is automatically picked based on the target and the atomic width:

Target Level Level for u64/i64
thumbv4t Full1 Full
thumbv6m CAS Full
thumbv7*, thumbv8* Native Full
riscv32imc Full1 Full
riscv32imac Native Full
xtensa-*-espidf Native Native
xtensa-esp32-* Native Full
xtensa-esp32s2-* Full Full
xtensa-esp32s3-* Native Full
xtensa-esp8266-* Cas Full
AVR Full Full

1: The hardware is capable of supporting atomic load/stores up to 32 bits, so this could be "CAS" instead of "Full". However, support for this is missing in Rust. See discussion here.

For targets not listed above, atomic-polyfill assumes nothing and reexports core::sync::atomic::*. No polyfilling is done. PRs for polyfilling more targets are welcome :)

Note: polyfill is based on critical sections using the critical-section crate. The default implementation is based on disabling all interrupts, so it's unsound on multi-core targets. It is possible to supply a custom critical section implementation, check the critical-section docs for details.


This work is licensed under either of

at your option.


Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any additional terms or conditions.