#atomic

nightly no-std atomic-maybe-uninit

Atomic operations on potentially uninitialized integers

9 releases

Uses new Rust 2021

new 0.2.9 Jun 30, 2022
0.2.8 Jun 21, 2022
0.2.5 May 30, 2022
0.2.4 Mar 20, 2022
0.1.0 Mar 12, 2022

#400 in Concurrency

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atomic-maybe-uninit

crates.io docs.rs license rustc build status build status

Atomic operations on potentially uninitialized integers.

Motivation

Copying types containing uninitialized bytes (e.g., padding), via the standard library's atomic types is undefined behavior because the copy goes through integers.

This crate provides a way to soundly perform such operations.

Platform Support

Currently, x86, x86_64, ARM (v6-m, v7+), AArch64, RISC-V, MIPS32r2, MIPS64r2, PowerPC, and s390x are supported.

target_arch primitives load/store swap CAS
x86 isize,usize,i8,u8,i16,u16,i32,u32,i64,u64 ✓[1]
x86_64 isize,usize,i8,u8,i16,u16,i32,u32,i64,u64
x86_64 (+cmpxchg16b) i128,u128
arm (v6-m, v7+) isize,usize,i8,u8,i16,u16,i32,u32 ✓[1] ✓[1]
arm (v7-a) i64,u64
aarch64 [2] isize,usize,i8,u8,i16,u16,i32,u32,i64,u64,i128,u128
riscv32 isize,usize,i8,u8,i16,u16,i32,u32 ✓[1] ✓[1]
riscv64 isize,usize,i8,u8,i16,u16,i32,u32,i64,u64 ✓[1] ✓[1]
mips [3] isize,usize,i8,u8,i16,u16,i32,u32
mips64 [3] isize,usize,i8,u8,i16,u16,i32,u32,i64,u64
powerpc [3] isize,usize,i8,u8,i16,u16,i32,u32
powerpc64 [3] isize,usize,i8,u8,i16,u16,i32,u32,i64,u64
powerpc64 (le or pwr8+) [3] [4] i128,u128
s390x [3] isize,usize,i8,u8,i16,u16,i32,u32,i64,u64,i128,u128

[1] ARM's atomic RMW operations are not available on v6-m (thumbv6m). RISC-V's atomic RMW operations are not available on targets without the A (or G) extension such as riscv32i, riscv32imc, etc. x86's atomic CAS is not available on i386 (80386).
[2] If target features such as lse and lse2 are enabled at compile-time, more efficient instructions are used.
[3] Requires nightly due to #![feature(asm_experimental_arch)].
[4] target-cpu pwr8, pwr9, or pwr10.

Feel free to submit an issue if your target is not supported yet.

Related Projects

License

Licensed under either of Apache License, Version 2.0 or MIT license at your option.

Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any additional terms or conditions.

No runtime deps