#atomic #uninitialized #operations #integer #no-alloc #copying #byte

nightly no-std atomic-maybe-uninit

Atomic operations on potentially uninitialized integers

15 releases

0.3.2 Jul 10, 2024
0.3.1 Oct 14, 2023
0.2.22 Aug 15, 2023
0.2.19 Jul 27, 2023
0.2.4 Mar 20, 2022

#385 in Concurrency

Apache-2.0 OR MIT

1MB
15K SLoC

atomic-maybe-uninit

crates.io docs.rs license msrv github actions cirrus ci

Atomic operations on potentially uninitialized integers.

Motivation

Copying types containing uninitialized bytes (e.g., padding), via the standard library's atomic types is undefined behavior because the copy goes through integers.

This crate provides a way to soundly perform such operations.

Platform Support

Currently, x86, x86_64, ARM, AArch64, RISC-V, LoongArch64, MIPS32, MIPS64, PowerPC, s390x, MSP430, Arm64EC, AVR, and Hexagon are supported.

target_arch primitives load/store swap/CAS
x86 isize,usize,i8,u8,i16,u16,i32,u32,i64,u64
x86_64 isize,usize,i8,u8,i16,u16,i32,u32,i64,u64
x86_64 (+cmpxchg16b) [5] i128,u128
arm (v6+ or Linux/Android) isize,usize,i8,u8,i16,u16,i32,u32 ✓[1]
arm (except for M-profile) [2] i64,u64
aarch64 isize,usize,i8,u8,i16,u16,i32,u32,i64,u64,i128,u128
riscv32 isize,usize,i8,u8,i16,u16,i32,u32 ✓[1]
riscv64 isize,usize,i8,u8,i16,u16,i32,u32,i64,u64 ✓[1]
loongarch64 [3] isize,usize,i8,u8,i16,u16,i32,u32,i64,u64
mips / mips32r6 [4] isize,usize,i8,u8,i16,u16,i32,u32
mips64 / mips64r6 [4] isize,usize,i8,u8,i16,u16,i32,u32,i64,u64
powerpc [4] isize,usize,i8,u8,i16,u16,i32,u32
powerpc64 [4] isize,usize,i8,u8,i16,u16,i32,u32,i64,u64
powerpc64 (pwr8+) [4] [6] i128,u128
s390x [4] isize,usize,i8,u8,i16,u16,i32,u32,i64,u64,i128,u128
msp430 [4] isize,usize,i8,u8,i16,u16
arm64ec [4] (experimental) isize,usize,i8,u8,i16,u16,i32,u32,i64,u64,i128,u128
avr [4] (experimental) isize,usize,i8,u8,i16,u16
hexagon [4] (experimental) isize,usize,i8,u8,i16,u16,i32,u32,i64,u64

[1] ARM's atomic RMW operations are not available on v6-m (thumbv6m). RISC-V's atomic RMW operations are not available on targets without the A (or G which means IMAFD) extension such as riscv32i, riscv32imc, etc.
[2] ARMv6+ or Linux/Android, except for M-profile architecture such as thumbv6m, thumbv7m, etc.
[3] Requires Rust 1.72+.
[4] Requires nightly due to #![feature(asm_experimental_arch)].
[5] Requires cmpxchg16b target feature (enabled by default on Apple and Windows (except Windows 7) targets).
[6] Requires target-cpu pwr8+ (powerpc64le is pwr8 by default).

Feel free to submit an issue if your target is not supported yet.

License

Licensed under either of Apache License, Version 2.0 or MIT license at your option.

Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any additional terms or conditions.

No runtime deps