#bitstream #xilinx #eda #cpld #coolrunner

bin+lib xc2bit

A library for working with Xilinx Coolrunner-II bitstreams

5 releases

0.0.4 Mar 15, 2020
0.0.3 May 13, 2018
0.0.2 Jun 24, 2017
0.0.1 Jun 16, 2017
0.0.0 Jun 6, 2017

#947 in Parser implementations


Used in xc2par

BSD-2-Clause

710KB
15K SLoC

xc2bit: A library for working with Xilinx Coolrunner-II bitstreams

xc2bit is a library for reading and writing bitstreams for the Xilinx Coolrunner-II family of CPLD devices.

This project is the result of a reverse-engineering effort involving a combination of imaging physical CPLD devices and black-box reverse-engineering of generated .jed files. It is not an official project of Xilinx, Inc. and is not affiliated or endorsed by Xilinx, Inc.

Logically, a Coolrunner-II CPLD contains the following major blocks: function blocks (occasionally abbreviated to FBs), a global interconnect (occasionally referred to as the ZIA or the AIM), and input/output blocks (occasionally abbreviated to IOBs). Function blocks are further divided into the PLA (programmable logic array, a matrix of AND and OR gates) and macrocells. In the Coolrunner-II architecture, macrocells also contain an XOR gate and a register. The global interconnect accepts inputs from IOBs and function blocks and connects these inputs into the PLA of each function block. IOBs also have direct connections to a corresponding macrocell in a function block. (The reverse is not always true - on larger devices, there are macrocells that are not connected to IOBs.) As a special exception, the smallest 32-macrocell devices also have one single input-only pin that is connected directly into the global interconnect and does not have a corresponding macrocell.

Dependencies

~1–1.7MB
~39K SLoC