Assembly Intermediate Representation (AIR)

This IR's purpose to model the semantics of assembly languages without delving into the detail of architectures.

Example

Currently, AIR looks like this:

arch:
  # define the pointer type of the current architecture
  ptr: i64
  # define the CPU registers and their type
  regs:
    "x0": i64
    "x1": i64
  # here, the user can define architecture-specific instructions 
  instructions:
    pacia:
      ty: i64
      operands: i64, i64

entry:
  v0 = i64.read_reg "x0"
  v1 = arch.pacia v0, 0x2a
  i64.write_reg v1, "x0"
  v2 = i64.read_reg "x1"
  v3 = i64.icmp.eq v2, 0x0
  jumpif v3, block1, block2

block1:
  ret

block2:
  trap

The above code roughly corresponds to something like this:

  pacia x0, #0x2a
  cmp x1, #0
  bne block2
  ret

block2:
  udf # unconditionally trap

lib.rs:

Assembly Intermediate Representation (AIR)