#startup #risc-v #run-time

no-std picorv32-rt

Minimal runtime / startup for PicoRV32 RISC-V CPU

4 releases

0.5.3 Aug 14, 2019
0.5.2 Aug 2, 2019
0.5.1 Aug 2, 2019
0.5.0 Jul 12, 2019

#31 in #startup

ISC license

41KB
667 lines

Contains (static library, 2KB) riscv32i-unknown-none-elf_RV32RT_INTERRUPTS_QREGS.a, (static library, 2KB) riscv32i-unknown-none-elf_RV32RT_BARE.a, (static library, 2KB) riscv32i-unknown-none-elf_RV32RT_INTERRUPTS.a, (static library, 2KB) riscv32ic-unknown-none-elf_RV32RT_BARE.a, (static library, 2KB) riscv32ic-unknown-none-elf_RV32RT_INTERRUPTS.a, (static library, 2KB) riscv32ic-unknown-none-elf_RV32RT_INTERRUPTS_QREGS.a

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picorv32-rt

(Very) minimal runtime / startup for PicoRV32 RISCV CPU.

This project is developed and maintained by the RISCV team.

Documentation

License

Copyright 2018 RISCV team

Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted, provided that the above copyright notice and this permission notice appear in all copies.

THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

Code of Conduct

Contribution to this crate is organized under the terms of the Rust Code of Conduct, the maintainer of this crate, the RISCV team, promises to intervene to uphold that code of conduct.

Dependencies

~3MB
~65K SLoC