#table #sequential #pin #cell #input #compiled #truth

logiclib

VLSI compiled logic library for sequential and combinational cells

5 releases

0.2.3 Dec 22, 2022
0.2.2 Nov 12, 2022
0.2.1 Nov 11, 2022
0.2.0 Oct 31, 2022
0.1.0 Oct 31, 2022

#5 in #truth

AGPL-3.0-only

38KB
745 lines

A logic library containing the compiled truth tables of a VLSI cell library.

We accept parsed Liberty file (libertyparse::Liberty) as input, and will output a flattened truth table list.

The truth table is special in that:

  1. The truth table is related to every output pin, instead of every cell.
  2. Both sequential and combinational elements can be modeled. Sequential elements have internal states. The state transition can be either modeled by R/F events (e.g., flip-flops), or pure 0/1 states (e.g., latches), or any their combination.
  3. There are 5 basic states: 0, 1, X, Z, UNK. UNK stands for unknown input. In reality, it can be any of 0, 1, X, Z. For FF clock pins, we have 7 basic states, the above 5 + R, F.

Dependencies

~4–13MB
~163K SLoC