#framework #chip #vlsi #eda #place-and-route

libreda-pnr

Algorithm interface definitions of the LibrEDA place-and-route framework

2 releases

0.0.4 Jul 13, 2022
0.0.0 Feb 22, 2021

#987 in Algorithms

AGPL-3.0-or-later

120KB
2K SLoC

Libreda PnR

Interface definitions for place-and-route algorithms of the LibrEDA framework.


lib.rs:

ASIC place-and-route framework.

This crate contains interface definitions for place-and-route related algorithms.

The core idea of the framework is to enable independent development of place & route engines which then can easily be plugged together.

Overview

Incomplete overview:

  • place - interfaces for placement engines and representations of placement problems
  • rebuffer - interface for buffer insertion engines
  • route - interfaces for routing engines
  • timing_analysis - interfaces for static timing-analysis (STA) engines
  • util - useful functions which don't yet have their own category

Dependencies

~3.5MB
~74K SLoC