#cad #eda #vlsi #data-structures

libreda-db

Layout and netlist datastructures for chip design

7 releases

0.0.12 Jun 5, 2024
0.0.11 Jun 4, 2024
0.0.10 Jul 13, 2022
0.0.9 Mar 14, 2022
0.0.4 Feb 22, 2021

#5 in #cad

41 downloads per month
Used in 6 crates

AGPL-3.0-or-later

310KB
6.5K SLoC

LibrEDA DB

LibrEDA DB is a collection of interface definitions and data structures for chip layouts and netlists.

Documentation

To view the documentation of this library in a browser clone this repository and run cargo doc --open.

Alternatively a possible outdated version is hosted here or here.

Current state

Most important functionality for handling layouts and netlists is already there. But this is still WORK IN PROGRESS and not stable yet.

Known shortcomings & ideas for future work

  • Provide a way to check if an ID is valid. For example with non-panicking .try_*() -> Option<*> functions.
  • Power domains: There's not a good way yet to represent power domains.
  • Region search: Implement region search as a decorator for LayoutEdit/LayoutBase traits.
  • Modification observer: Implement a decorator which allows to observe modifications on database structures using callback functions.

Dependencies

~4.5MB
~88K SLoC