#vlsi #eda #cad

libreda-db

Layout and netlist datastructures for chip design

5 releases

Uses new Rust 2021

0.0.10 Jul 13, 2022
0.0.9 Mar 14, 2022
0.0.8 Dec 10, 2021
0.0.6 Oct 15, 2021
0.0.4 Feb 22, 2021

#236 in Data structures

Download history 17/week @ 2022-07-28 28/week @ 2022-08-04 25/week @ 2022-08-11 13/week @ 2022-08-18 19/week @ 2022-08-25 21/week @ 2022-09-01 38/week @ 2022-09-08 9/week @ 2022-09-15 23/week @ 2022-09-22 34/week @ 2022-09-29 30/week @ 2022-10-06 4/week @ 2022-10-13 14/week @ 2022-10-20 31/week @ 2022-10-27 32/week @ 2022-11-03 26/week @ 2022-11-10

103 downloads per month
Used in 5 crates

AGPL-3.0-or-later

305KB
5K SLoC

LibrEDA DB

LibrEDA DB is a collection of interface definitions and data structures for chip layouts and netlists.

Documentation

To view the documentation of this library in a browser clone this repository and run cargo doc --open.

Alternatively a possible outdated version is hosted here or here.

Current state

Most important functionality for handling layouts and netlists is already there. But this is still WORK IN PROGRESS and not stable yet.

Known shortcomings & ideas for future work

  • Provide a way to check if an ID is valid. For example with non-panicking .try_*() -> Option<*> functions.
  • Power domains: There's not a good way yet to represent power domains.
  • Region search: Implement region search as a decorator for LayoutEdit/LayoutBase traits.
  • Modification observer: Implement a decorator which allows to observe modifications on database structures using callback functions.

Dependencies

~1.3–2MB
~41K SLoC