#risc-v #wrapper #api-bindings #instructions #disassembler #spike-dasm #disasm

spike-dasm-wrapper

RISC-V instruction disassembler based on spike-dasm

2 releases

0.0.2 Sep 30, 2020
0.0.1 Sep 30, 2020

#38 in #disassembler

MIT/Apache

1MB
21K SLoC

C 12K SLoC // 0.4% comments C++ 9K SLoC // 0.0% comments Shell 210 SLoC // 0.3% comments M4 165 SLoC // 0.6% comments Python 116 SLoC // 0.0% comments Rust 67 SLoC GNU Style Assembly 50 SLoC // 0.3% comments

Contains (autotools obfuscated code, 185KB) riscv-isa-sim/configure, (obscure autoconf code, 5KB) riscv-isa-sim/configure.ac

spike-dasm-wrapper

spike-dasm-wrapper is wrapper of spike-dasm in riscv-isa-sim.

Usage

[dependencies]
spike-dasm-wrapper = "0.0.2"

Example

use spike_dasm_wrapper::{Disasm};

fn main() {
	let mut disasm = Disasm::new();

	let dis_str = disasm.disassemble(0x0000_0000);
	assert_eq!(dis_str, "c.addi4spn s0, sp, 0");

	let dis_str = disasm.disassemble(0x01c28293);
	assert_eq!(dis_str, "addi    t0, t0, 28");

	let dis_str = disasm.disassemble(0x4201);
	assert_eq!(dis_str, "c.li    tp, 0");
}

License

Licensed under either of

at your option.

Contribution

Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any additional terms or conditions.

No runtime deps