#risc-v #encode #vector #macro #rvv

macro rvv-asm

Procedure macro to encode RISC-V V extension (rvv) instructions

14 releases

0.2.1 Jul 28, 2022
0.2.0 Jul 6, 2022
0.1.13 Apr 28, 2022
0.1.11 Feb 14, 2022
0.1.9 Jan 25, 2022

#535 in Procedural macros

MIT license

155KB
3K SLoC

Example usage

unsafe {
    rvv_asm::rvv_asm!(
        "vsetvl x5, s3, t6",
        "1: vle256.v v3, (a0), vm",
        "2:",
        "li {lo}, 4",
        lo = out(reg) lo,
    );
}

Dependencies

~3MB
~60K SLoC