riscv_vcpu

riscv64 virtual CPU (vCPU) implementation for hypervisors. This crate provides the core vCPU structure and virtualization-related interface support specifically designed for the riscv64 architecture.

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Overview

riscv_vcpu implements a minimal RISC-V Virtual CPU (VCPU) abstraction layer compliant with the RISC-V Hypervisor Extension (RVH). Designed for embedded hypervisors and educational use, it can operates in no_std environments.

Features

• Complete vCPU Implementation: Full virtual CPU structure for riscv64 guests
• Exception Handling: Comprehensive trap and exception handling for virtualized environments
• EPT (Extended Page Tables): Memory virtualization support
• VMCS Management: Virtual Machine Control Structure operations
• Per-CPU Support: Efficient per-CPU data structures and management
• No-std Compatible: Works in bare-metal and embedded environments

Usage

Add this to your Cargo.toml:

[dependencies]
riscv_vcpu = "0.1"

Basic Usage

use riscv_vcpu::{RISCVVCpu, RISCVVCpuCreateConfig, has_hardware_support};

// Check if hardware virtualization is supported
if has_hardware_support() {
    // Create vCPU configuration
    let config = RISCVVCpuCreateConfig::default();
    
    // Create and configure the virtual CPU
    let vcpu = RISCVVCpu::new(config)?;
    
    // Run the virtual CPU
    vcpu.run()?;
}

Related Projects

• ArceOS - An experimental modular OS (or Unikernel)
• AxVisor - Hypervisor implementation

License

This project is dual-licensed under either:

• MIT License (LICENSE-MIT or http://opensource.org/licenses/MIT)
• Apache License, Version 2.0 (LICENSE-APACHE or http://www.apache.org/licenses/LICENSE-2.0)

at your option.