Rust RISC-V ISA crate

Rust crate for working with the RISC-V instruction set architecture.

This library currently supports decoding RISC-V instructions and has partial support for producing disassembly.

Instructions from the following specs and extensions are supported:

• RV32I
• RV64I
• M
• A
• F
• D
• Q
• C
• B
• Zifencei
• Zicsr
• Zawrs
• Zfh
• Zba
• Zbb
• Zbc
• Zbs
• Zbkb

License

This work is distributed under the terms of both the MIT license and the Apache-2.0 license. See LICENSE-APACHE and LICENSE-MIT for details.

lib.rs:

RISC-V instruction set architecture library.

Supports decoding RV32I and RV64I instructions with a variety of extensions:

• M
• A
• C
• F
• D
• Q
• Zifencei
• Zicsr
• Zawrs
• Zba, Zbb, Zbc, Zbs
• Zbkb

Example

use std::str::FromStr;
use riscv_isa::{Decoder, Instruction, Target};

let target = Target::from_str("RV32IMACZifencei_Zicsr").unwrap();
let instructions = [
    0x83, 0xa2, 0xad, 0x00, // lw x5, 10(x27)
    0x33, 0x82, 0x78, 0x03, // mul x4, x17, x23
];

let mut decoder = Decoder::from_le_bytes(target, &instructions[..]);

assert_eq!(decoder.next(), Some(Instruction::LW { rd: 5, rs1: 27, offset: 10 }));
assert_eq!(decoder.next(), Some(Instruction::MUL { rd: 4, rs1: 17, rs2: 23 }));
assert_eq!(decoder.next(), None);