Osiris/Process

• 64 bits fixed-width instruction :
  • 16 bits operation identifier,
  • 16 bits target register
  • 32 bits optional argument(s),
• 64 bits wide addresses,
• range-based register operations.

License

• Copyright (c) 2024 Sébastien Geldreich
• License MIT

lib.rs:

This crate provides structs and implementation to help create virtual machines :

• addressed on 64-bits,
• with 64-bits length operations,
• operating on 64-bits words.

It is not ready for production, it may evolve a lot !

An example (WIP) implementation.

It makes some opinionated choices like :

• Having 65536 general-registers (register::integral::Bank) per processor::Cpu,
• Having 65536 floating-point registers (register::floating_point::Vector),
• operation::Operations are meant to operate on a range of registers,
• Neither the ordering or the invocation of processors nor the operation sets are implemented in this crate.