Lib.rs

Cargo Features

esp-riscv-rt has no features set by default.

[dependencies]
esp-riscv-rt = { version = "0.8.0", features = ["fix-sp", "has-mie-mip", "init-data", "init-rtc-fast-data", "init-rtc-fast-text", "init-rw-text", "zero-bss", "zero-rtc-fast-bss", "ci"] }

fix-sp ci?

Move the stack to the start of RAM to get zero-cost stack overflow protection (ESP32-C6 and ESP32-H2 only!)

has-mie-mip ci?

Indicate that the device supports mie and mip instructions.

init-data ci?

Memory Initialization Feature Flags

Initialize the data section.

init-rtc-fast-data ci?

Initialize the .rtc_fast.data section.

init-rtc-fast-text ci?

Initialize the .rtc_fast.text section.

init-rw-text ci?

Initialize the .rwtext section.

zero-bss ci?

Zero the .bss section.

zero-rtc-fast-bss ci?

Zero the .rtc_fast.bss section.

ci = fix-sp, has-mie-mip, init-data, init-rtc-fast-data, init-rtc-fast-text, init-rw-text, zero-bss, zero-rtc-fast-bss

This feature is intended for testing; you probably don't want to enable it: